1. Field of the Invention
The present invention relates to a gate line drive circuit for driving a gate line of a display device.
2. Description of Related Art
Display devices such as a TFT-LCD (Thin Film Transistor-Liquid Crystal Display), a passive matrix liquid crystal display, an electroluminescence (EL) display, and a plasma display have been widely spread. The TFT-LCD will be explained as an example of the above-mentioned display devices.
In the TFT-LCD, a timing controller, for example, supplies a gate line address signal for selecting a selection gate line from N gate lines to a gate line drive circuit in one horizontal period. N is 2 raised to the power n, where n is a positive integer. The gate line drive circuit supplies a first driving voltage VGH for driving the selection gate line to the selection gate line based on the gate line address signal, and supplies a second driving voltage VGL for not driving non-selection gate lines that are gate lines other than the selection gate line to the non-selection gate lines. The second driving voltage VGL is lower than the first driving voltage VGH. In this case, the first driving voltage VGH is transmitted from one end to the other end of the selection gate line, and TFTs (Thin Film Transistors) of pixels corresponding to the selection gate line are turned on based on the first driving voltage supplied to the gate electrodes of the TFTs.
The above-mentioned gate line address signal includes N address signals. One address signal of the N address signals represents a first voltage VDD for selecting the selection gate line, and each of the other address signals represents a second voltage VCC for selecting the non-selection gate line. The second voltage VCC is lower than the first voltage VDD. The first voltage VDD generally represents a voltage of approximately 1 to 5 [V], the second voltage VCC represents, for example, 0 [V] as a ground voltage. In addition, the above-mentioned first driving voltage VGH and the second driving voltage VGL are approximately 20 [V] and −20 [V], respectively. Accordingly, the gate line drive circuit requires N level shift circuits for converting the first voltages VDD and the second voltages VCC of the N address signals into the first driving voltages VGH and the second driving voltages VGL.
The N level shift circuits are provided corresponding to the number of the gate lines, N, and each of the level shift circuits includes transistors. High-voltage transistors are required to be employed as the transistors. FIG. 1 shows a level shift circuit as an example. Each of the N level shift circuits includes, for example, a two-stage differential amplifier. The two-stage differential amplifier includes ten of high-voltage transistors P11, P12, N11, N12, N13, N14, P21, P22, N21, and N22.
However, the high-voltage transistor occupies a larger area than a low-voltage transistor which is, for example, used for a logic gate. For this reason, when the gate line drive circuit is formed on a chip, the level shift circuit occupies a large area in a whole area of the chip. In addition, in accordance with the number of gate lines, N, many high-voltage transistors are used. The larger the number of the high-voltage transistors is, the much larger area the level shift circuit occupies.
Accordingly, it is desired to reduce a ratio of the number of the level shift circuits to the number of the gate lines, N.
FIG. 2 shows a gate line drive circuit 120 as a gate line drive circuit described in Japanese Laid Open Patent Application (JP-P2002-215119A).
The gate line drive circuit 120 includes a gate line logic circuit 124, a first level shift circuit module 126, a second level shift circuit module 128, and a multiplexer 122. N gate lines G_1 to G_N are grouped into L groups GR_1 to GR_L each of which includes K gate lines. A relation among N, K, and L is given by N=L×K.
The gate line logic circuit 124 outputs, as signals corresponding to the above-mentioned gate line address signal, K scan signals SR_1 to SR_K to the first level shift circuit module 126 and L pairs of control signals C_1, C_1′ to C_L, C_L′ to the second level shift circuit module 128. The L control signals C_1′ to C_L′ are inversion signals of the L control signals C_1 to C_L. The gate line logic circuit 124 outputs the L pairs of control signals C_1, C_1′ to C_L, C_L′ to the second level shift circuit module 128 in the order from a first pair of control signals C_1 and C_1′ to an L-th pair of control signals C_L and C_L′. In addition, the gate line logic circuit 124 outputs the K scan signals SR_1 to SR_K to the first level shift circuit module 126 in the order from the first scan signal SR_1 to the K-th scan signal SR_K while outputting each pair of the L pairs of control signals C_1, C_1′ to C_L, and C_L. The K scan signals SR_1 to SR_K represent, for example, the above-mentioned first voltage VDD.
The first level shift circuit module 126 includes K level shift circuits LSD_1 to LSD_K and is supplied with a first driving voltage VGH. The K level shift circuits LSD_1 to LSD_K convert the first voltage VDD represented by the K scan signals SR_1 to SR_K into the first driving voltage VGH, and output the first driving voltage VGH as driving signals D_1 to D_K to the multiplexer 122.
The second level shift circuit module 128 includes L pairs of level shift circuits LSC_1, LSC_1′ to LSC_L, LSC_L′. The L pairs of level shift circuits LSC_1, LSC_1′ to LSC_L, LSC_L′ convert voltages represented by the L pairs of control signals C_1, C_1′ to C_L, C_L′ into predetermined voltages, and output the predetermined voltages to the multiplexer 122.
FIG. 3 shows the multiplexer 122. The multiplexer 122 includes N first transistors and N second transistors. For example, N-channel type MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) are employed as the first transistors and the second transistors. Sources of the N first transistors are respectively connected to the N gate lines G_1 to G_N and respectively connected to drains of the N second transistors. A second driving voltage VGL is supplied to sources of the N second transistors. The N first transistors and the N second transistors are grouped into L groups GR_1 to GR_L each of which includes K first transistors and K second transistors. Drains of the K first transistors are connected to the K level shift circuits LSD_1 to LSD_K of the first level shift circuit module 126, respectively. Gates of the respective first transistors of the L groups GR_1 to GR_L are connected to outputs of the L level shift circuits LSC_1 to LSC_L of the second level shift circuit module 128, and supplied with the L control signals C_1 to C_L, respectively. Gates of the respective second transistors of the L groups GR_1 to GR_L are connected to outputs of the L level shift circuits LSC_1′ to LSC_L′ of the second level shift circuit module 128, and supplied with the L control signals C_1′ to C_L′, respectively.
FIG. 4 is a timing chart showing an operation of the multiplexer 122. As a process with respect to the group GR_1, the multiplexer 122 receives the K scan signals SR_1 to SR_K from the first level shift circuit module 126 in the order from the first scan signal SR_1 to the K-th scan signal SR_K while receiving the first pair of control signals C_1 and C_1′ from the second level shift circuit module 128. In this case, the multiplexer 122 supplies the first driving voltage VGH to the K gate lines of the group GR_1 in the order from the first gate line to the K-th gate line, and supplies the second driving voltage VGL to the gate lines of the groups other than the group GR_1. By carrying out the same process with respect to the groups GR_2 to GR_L, the first driving voltage VGH is supplied to the N gate lines G_1 to G_N in the order from the first gate line to the N-th gate line.
As for the gate line drive circuit 120, the number of the level shift circuits used for driving the N gate lines G_1 to G_N is represented by 2×L+K. For example, given that N is 1024 and L is 8, K is 128 based on K=N/L. In this case, the number of the level shift circuits is 144 based on 2×L+K. In this manner, the ratio of the number of the level shift circuits to the number of the gate lines, N can be reduced.
In these years, as exemplified with respect to microcomputers or portable terminals, downsizings of chips and packages are increasingly demanded. In order to downsize the chips and the packages, reduction of a chip area is required.
As for the gate line drive circuit 120, the ratio of the number of the level shift circuits to the number the of gate lines, N is reduced, however, the (2×L+K) level shift circuits are still required. As described above, a plurality of high-voltage transistors are used in one level shift circuit and the high-voltage transistor occupies a larger area than a low-voltage transistor which is, for example, used for a logic gate. For example, in a chase that ten high-voltage transistors are used in each of the above-described 144 level shift circuits and the gate line drive circuit 120 including the 144 level shift circuits is formed on a chip, at least an area for 1440 high-voltage transistors is required in a whole area of the chip.
As described above, there is a room for further improvement in the above-mentioned gate line drive circuit.